| 00:27.04 | IriX64 | x11 server of a sorts is included as an installer archive(Xwin32) but it's commercial, sorta works, but i'm leaning to Xming, free and works better |
| 00:28.54 | IriX64 | remember it's 7.8.4 |
| 00:32.35 | IriX64 | http://www.straightrunning.com/XmingNotes/ Xming can be had here. should work better |
| 00:53.50 | *** join/#brlcad louipc (n=louipc@bas8-toronto63-1177705505.dsl.bell.ca) | |
| 01:14.23 | IriX64 | no ls in that one though ;) |
| 01:21.52 | louipc | <PROTECTED> |
| 01:21.54 | *** part/#brlcad louipc (n=louipc@bas8-toronto63-1177705505.dsl.bell.ca) | |
| 01:23.05 | IriX64 | http://irix32.spaces.live.com/photos windowsside |
| 02:00.29 | brlcad | aww, 7.8.4 is not useful.. :) |
| 02:38.20 | brlcad | should get 7.10 to work... 7.8 is history |
| 02:43.55 | IriX64 | working on that now:) |
| 02:44.09 | brlcad | cool |
| 02:45.00 | IriX64 | thanks... for looking at it |
| 02:46.06 | IriX64 | 7.10 is quite a bit bigger... almost 1gig zip file |
| 03:40.50 | IriX64 | see why i don't want commit access, I shot my big toe off again :) |
| 04:15.59 | CIA-4 | BRL-CAD: 03brlcad * 10brlcad/autogen.sh: |
| 04:15.59 | CIA-4 | BRL-CAD: revert the stashing of COPYING and INSTALL into memory due to issues with a |
| 04:15.59 | CIA-4 | BRL-CAD: handful of shells/environments where it would cause unpredictable shell |
| 04:15.59 | CIA-4 | BRL-CAD: behavior. instead, save backup files as needed (recursively). additional |
| 04:15.59 | CIA-4 | BRL-CAD: awesomeness, set up trap signal handlers to clean up regardless of how/when |
| 04:15.59 | CIA-4 | BRL-CAD: autogen.sh terminates or is otherwise aborted. |
| 04:43.04 | CIA-4 | BRL-CAD: 03brlcad * 10brlcad/TODO: update to a6, verify auto_path code more thoroughly |
| 05:33.49 | *** join/#brlcad SWPadnos_ (n=Me@dsl245.esjtvtli.sover.net) | |
| 06:17.27 | *** join/#brlcad clock_ (i=clock@84-72-88-220.dclient.hispeed.ch) | |
| 07:19.24 | *** join/#brlcad Rangar_ (n=dave@203.118.156.252) | |
| 07:19.51 | Rangar_ | Mal, Erik.. either of you around to fix ops in #gl? |
| 07:49.19 | *** join/#brlcad clock_ (n=clock@zux221-122-143.adsl.green.ch) | |
| 09:44.02 | *** join/#brlcad docelic (n=docelic@212.15.177.80) | |
| 10:33.51 | *** join/#brlcad clock_ (n=clock@zux221-122-143.adsl.green.ch) | |
| 10:51.16 | *** join/#brlcad clock_ (n=clock@zux221-122-143.adsl.green.ch) | |
| 11:15.41 | *** join/#brlcad gioacchino (n=gioacchi@host-84-220-19-231.cust-adsl.tiscali.it) | |
| 11:29.19 | *** join/#brlcad elite01 (n=elite01@dslb-088-070-030-021.pools.arcor-ip.net) | |
| 12:50.36 | *** join/#brlcad Elperion (n=Elperion@p54874C3A.dip.t-dialin.net) | |
| 12:56.06 | brlcad | should be soon |
| 13:04.18 | Rangar | thanks |
| 13:36.00 | *** join/#brlcad Bariton (n=Elperion@p5487706A.dip.t-dialin.net) | |
| 14:06.11 | *** join/#brlcad CIA-31 (n=CIA@208.69.182.149) | |
| 14:35.55 | CIA-31 | BRL-CAD: 03brlcad * 10brlcad/configure.ac: according to report from jra, BRLCAD_DATA is still getting set to NONE for his case, so rework the prefix settings once again to make sure there's a double eval on prefix and datadir before setting the AC_DEFINE's |
| 14:36.43 | clock_ | brlcad: even when a tiny screw is in the scene, the whole rendering gets many times slower |
| 14:36.56 | clock_ | brlcad: I am already compiling the Ronja for about a week... |
| 15:05.54 | *** join/#brlcad IriX64 (n=mario_du@bas2-sudbury98-1177871595.dsl.bell.ca) | |
| 15:14.07 | CIA-31 | BRL-CAD: 03brlcad * 10brlcad/NEWS: converters abort early on corrupted input geometry and a memory link in librtserver was fixed, both courtesy mister anderson |
| 15:18.44 | CIA-31 | BRL-CAD: 03brlcad * 10brlcad/src/conv/iges/.cvsignore: ignore iges binary |
| 15:47.19 | CIA-31 | BRL-CAD: 03brlcad * 10brlcad/configure.ac: oop, typo -- should be bc_data_dir var being checked |
| 15:52.03 | CIA-31 | BRL-CAD: 03brlcad * 10brlcad/NEWS: how the.. |
| 16:24.24 | IriX64 | ty :) |
| 16:44.07 | gioacchino | brlcad: ci sei ? |
| 18:03.17 | brlcad | gioacchino: sempre |
| 18:15.08 | gioacchino | heeheehehee |
| 18:44.25 | *** join/#brlcad clock_ (i=clock@84-72-88-220.dclient.hispeed.ch) | |
| 19:11.38 | *** join/#brlcad MinstrelGypsy (n=mario_du@bas2-sudbury98-1177871595.dsl.bell.ca) | |
| 19:41.49 | *** join/#brlcad docelic (n=docelic@212.15.177.80) | |
| 20:50.22 | CIA-31 | BRL-CAD: 03jlowenz * 10brlcad/src/conv/iges/BrepHandler.cpp: flesh out extraction methods using iges spec. |
| 20:52.49 | CIA-31 | BRL-CAD: 03jlowenz * 10brlcad/src/conv/iges/n_iges.cpp: implement methods needed for parameter handling and extraction code |
| 20:54.26 | CIA-31 | BRL-CAD: 03jlowenz * 10brlcad/src/conv/iges/n_iges.hpp: consolidate brep handling into one class (since the elements are interdependent) |
| 20:56.27 | CIA-31 | BRL-CAD: 03jlowenz * 10brlcad/src/conv/iges/nmain.cpp: comment things out temporarily to get it to compile |
| 20:58.18 | CIA-31 | BRL-CAD: 03jlowenz * 10brlcad/src/conv/iges/Makefile.am: add brlcad_brep.cpp to source list |
| 21:50.56 | CIA-31 | BRL-CAD: 03brlcad * 10brlcad/autogen.sh: clean up after all backup files, starting from the source root |
| 21:51.11 | *** join/#brlcad jano (n=point@mailbox.nationalfranchisesales.com) | |
| 21:51.24 | *** part/#brlcad jano (n=point@mailbox.nationalfranchisesales.com) | |
| 21:58.56 | *** join/#brlcad MinstrelGypsy (n=mario_du@bas2-sudbury98-1177871595.dsl.bell.ca) | |
| 21:59.55 | *** join/#brlcad b0ef (n=b0ef@084202026226.customer.alfanett.no) [NETSPLIT VICTIM] | |
| 21:59.56 | *** join/#brlcad elite01 (n=elite01@dslb-088-070-030-021.pools.arcor-ip.net) [NETSPLIT VICTIM] | |
| 22:00.36 | MinstrelGypsy | brlcad: figured out why it's so big, forgot to do --disable-shared. |
| 22:05.38 | MinstrelGypsy | http://irix32.spaces.live.com/photos windowsside terra.g :) |
| 22:07.00 | *** join/#brlcad Twingy (n=justin@74.92.144.217) | |
| 22:30.08 | *** join/#brlcad Rangar (n=dave@203.118.156.252) [NETSPLIT VICTIM] | |
| 22:30.09 | *** join/#brlcad elite01 (n=elite01@88.70.30.21) [NETSPLIT VICTIM] | |
| 22:30.10 | *** join/#brlcad SWPadnos_ (n=Me@dsl245.esjtvtli.sover.net) | |
| 22:36.11 | CIA-31 | BRL-CAD: 03brlcad * 10brlcad/src/conv/iges/nmain.cpp: there is no brlcad.hpp |
| 22:36.55 | CIA-31 | BRL-CAD: 03brlcad * 10brlcad/src/conv/iges/Makefile.am: there is no brlcad_brep.cpp |
| 22:39.16 | CIA-31 | BRL-CAD: 03brlcad * 10brlcad/misc/Makefile.defs: remove EXTRA_PROGRAMS too on prodclean |
| 22:42.30 | CIA-31 | BRL-CAD: 03brlcad * 10brlcad/src/conv/iges/Makefile.am: do not build the 'iges' binary being developed by default at all, can still be built directly with 'make iges' |